1. Field of the Invention
The present invention relates to a wafer level packaging of a semiconductor chip. More particularly, the present invention relates to a wafer level packaging cap for the wafer level packaging and fabrication method thereof.
2. Description of the Related Art
Generally, devices manufactured as a chip unit and performing certain functions are extremely vulnerable to damage from moisture, small particles, and high temperature, and therefore, need to be packaged. Examples of the devices include microscopic mechanisms such as Integrated Circuit (IC), Hybrid chip for communication, Radio Frequency Micro Electro Mechanical System (RF MEMS), and an actuator. For the package, a top surface of a device wafer with a device performing certain functions is covered and hermetically sealed with a cap having a cavity providing a space capable of receiving the device. A “wafer level packaging” means that, prior to dicing the wafer with a plurality of devices into individual chips, the wafer is hermetically sealed and packaged with a packaging cap to form a wafer unit and diced into individual chips. The wafer level packaging is also applied to producing devices such as charge-coupled device (CCD), sensor which needs to minimize exposure to high temperature, moisture, gas materials, and particles. Hereinafter, the packaging cap for the wafer level packaging will be explained as a chip unit for convenience.
FIG. 1 is a view of an example of a chip packaged with a conventional wafer level packaging cap.
Referring to FIG. 1, a packaged chip 1 comprises a device wafer 10 and a packaging cap 20.
The device wafer 10 comprises a device substrate 11, a device 12 formed at a top surface of the device substrate 11 and performing a certain function, and a plurality of device pads 13 electrically connected with the device 12, and is manufactured according to a general semiconductor fabrication process.
The packaging cap 20 comprises a cap substrate 21 having at the bottom surface a cavity 22 of a certain volume providing a space for receiving the device 12 and integrally packaged with the device wafer 10, a plurality of metal lines 25 formed from the bottom surface of the cap substrate 21 to an inner surface 22a of the cavity 22 to correspond to a plurality of the device pads 13 (electrically connected to the device 12), a plurality of connection holes 28 penetrating from the inner surface 22a of the cavity 22 of the cap substrate 21 to the top surface of the cap substrate 21 to correspond to the metal lines 25, a plurality of connection rods 24 formed in the plurality of the connection holes 28, and from the bottom portion electrically connected to the plurality of metal lines 25, and a plurality of cap pads 23 formed at the top surface of the cap substrate 21 and electrically connected to top portions of the connection rods 24 of the plurality of connection holes 28.
A sealing line 14 of the device wafer 10 and a cap sealing line 27 of the packaging cap 20 are melted and bonded by eutectic bonding to complete the packaging of the chip 1.
According to conventional art, however, plenty of damages occur around the connection holes 28 of the packaging cap 20 during a temperature resistance test. This is because of a thermal stress during heating for the temperature resistance test, caused by difference of heat strain ratio between a material of the wafer of the cap substrate 21 forming the connection holes 28 and a material forming the connection rod 24. As such, it is necessary to buffer the stress.
To this end, the plurality of connection holes 28 are manufactured on the cap substrate 21, a buffer material layer is formed on the inner surface of the connection holes 28, and then the connection rods 24 are formed by electroplating. For the electroplating, a seed metal layer needs to be formed on the buffer material layer of the inner surface of the connection holes 28. Generally, it is possible to form the seed metal layer on the inner surface of the connection holes 28 only when the depth of the connection holes is less than 100 μm. In other words, the seed metal layer can be formed only on the connection holes 28 formed in the wafer with the thickness of less than 100 μm. However, the thickness of the completely-manufactured cap substrate 21 must be generally 300 μm or more in view of mechanical characteristics of the wafer and convenience of manufacturing. If the cap substrate 21 is thinner than 300 μm, the wafer may be easily damaged during manufacture process. Accordingly, it is impossible to form the seed metal layer on the connection holes 28 of the cap substrate 21 with thickness of 300 μm or more according to the above method. If the seed metal layer can not be formed, the electroplating can not be performed, and therefore, it is impossible to form the connection rods 24.
According to the conventional fabrication method of the packaging cap, it is difficult to form the buffer material in the connection holes 28 in order to have good features during the temperature resistance test for the wafer with the thickness of 300 μm or more.